For the operation of integrated circuits, power must be supplied and distributed appropriately. This requires the appropriate distribution of operation voltages VDD and VSS. FIG. 1, which is a top view of a semiconductor chip, illustrates a power distribution scheme for distributing operation voltages VDD and VSS throughout a chip. VDD lines 10, which form a mesh, are distributed throughout the respective chip and carry operation voltage VDD. VSS lines 14, which also form a mesh, are distributed throughout the respective chip and carry operation voltage VSS. VDD pads 12 and VSS pads 16 are formed on the top surface of the respective semiconductor chip to receive the VDD and VSS voltage, respectively, from outside the chip.
With advanced technologies for forming circuits having small sizes, the design complexity is increased dramatically, which leads to a high power dissipation. Accordingly, a large number of power pads 12 and 16 are required for internal circuit current supply. In addition, a dense power mesh is needed for minimizing IR drop. Due to pad-pitch limitations, the sizes of pads 12 and 16 cannot be reduced, and a great amount of chip area, which may be as great as 20 to 30 percent or even greater, is occupied by power pads 12 an 16. In addition, a significant amount of routing resource is taken by the power mesh. This results in a significant increase in the chip size as well as production cost.
FIG. 2 illustrates a cross-sectional view of a chip, which shows how power is supplied to transistors 28 through bump 18, power pads 12/16, power mesh 10/14, and the connecting metal lines 22 and vias 24. It is notice that the power needs to go through a plurality of metal lines and vias before reaching transistors 28. The effective resistance between power mesh 10/14 and transistors 28 thus includes the resistances of metal lines 22 and stacked vias 24, which may reach as high as tens of ohms. The voltage drop caused by current-resistance (IR) is hence high. An additional problem of the conventional power supply scheme as shown in FIGS. 1 and 2 is that stacked metal lines 22 and vias 24 occupy the chip area that otherwise would be used for routing, and hence they block the routing of signals and result in congestion.